Hi Shivam,
I am not quite sure what it is you are trying to do. Do you want to know the
addresses of TLB misses (page faults), or perhaps the accesses to DRAM rows
(pages) that are not in the row buffer? If it is the latter, then have a look
at src/mem/simple_dram.cc where you find the memory controller code, and more
specifically the scheduling and page policy. Is this what you are after?
Andreas
From: Shivam Agarwal
<[email protected]<mailto:[email protected]>>
Reply-To: gem5 users mailing list
<[email protected]<mailto:[email protected]>>
Date: Friday, 17 January 2014 18:44
To: gem5 users mailing list <[email protected]<mailto:[email protected]>>
Subject: [gem5-users] Cycle Accurate Page Faults from DRAM
Hi all
I need to get a trace of page misses from the main memory. Kindly tell how
can this be done in gem5.
Thanks
Shivam
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