Hi Andreas Thanks for your response. I need to keep track of page requests that go to the disk. If the page table is entirely contained in the TLB then I think TLB misses will serve my purpose. Can you please guide me where to look for this.
Regards Shivam On Mon, Jan 20, 2014 at 3:35 PM, Andreas Hansson <[email protected]>wrote: > Hi Shivam, > > I am not quite sure what it is you are trying to do. Do you want to know > the addresses of TLB misses (page faults), or perhaps the accesses to DRAM > rows (pages) that are not in the row buffer? If it is the latter, then have > a look at src/mem/simple_dram.cc where you find the memory controller code, > and more specifically the scheduling and page policy. Is this what you are > after? > > Andreas > > From: Shivam Agarwal <[email protected]> > Reply-To: gem5 users mailing list <[email protected]> > Date: Friday, 17 January 2014 18:44 > To: gem5 users mailing list <[email protected]> > Subject: [gem5-users] Cycle Accurate Page Faults from DRAM > > Hi all > I need to get a trace of page misses from the main memory. Kindly tell > how can this be done in gem5. > > Thanks > Shivam > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2557590 > ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2548782 > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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