Hi, I am running X86 architecture in SE mode. I am also using --Caches flag.
In the /common/Caches.py I set L1 cache latency (hit latency/ response_latency) to be 20 cycles or any value. When I run simulation, for every hit in L1 cache (I/D), In the log file generated using debug-flag Caches, every request to L1 and its response occur at the same tick value, which shows there is no effect of hit_latency How to add hit_latency for L1 cache or am I missing something. Regards, Aditya
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