Hello, The latency used is that informed in the config.ini file. It's a good starting point to check that.
Regards, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2014-02-10 18:22 GMT+01:00 Aditya Deshpande <[email protected]>: > Hi, > > I am running X86 architecture in SE mode. I am also using --Caches flag. > > In the /common/Caches.py > I set L1 cache latency (hit latency/ response_latency) to be 20 cycles or > any value. When I run simulation, for every hit in L1 cache (I/D), In the > log file generated using debug-flag Caches, every request to L1 and its > response occur at the same tick value, which shows there is no effect of > hit_latency > > How to add hit_latency for L1 cache or am I missing something. > > Regards, > Aditya > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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