Can you increase the cache size so that the cache miss rate is within 8% to see whether direct map cache still has lower cache miss rate?
Zhiguo -----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of Summer Sent: Wednesday, February 12, 2014 3:01 AM To: [email protected] Subject: [gem5-users] cache statistics Hi all, I am working on a project to improve the last level cache performance and we want to simulate 4 levels of cache in gem5. However, when I simulate using SPEC CPU 2006 on 1 timing cpu, higher associative L4 turns out higher miss rate. For example, a 256MB, 32 associative L4 gets miss rate 38.7% while 256MB, direct mapped L4 gets miss rate 20%. I am pretty confused by this result but I have tried several runs and got the same results. Does anyone have any idea about this? Your help is greatly appreciated! Best Regards _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
