Hello, Generally, the O3 pipeline stalls when the IQ, ROB or LSQ are full (controlled by the rename stage). If the Dcache is blocked (see http://www.gem5.org/docs/html/gem5MemorySystem.html), the pipeline still tries to access it and then squashes instructions that found the cache blocked. Then, the pipeline may finally stall when the above structures are full. Please correct if I'm wrong.
Hope it helps, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2014-03-17 14:06 GMT+01:00 Leonardo Ecco <[email protected]>: > How can I configure how many cache misses are required before the pipeline > is actually stalled? > I can't find the parameter that needs to be changed... > > (I'm using an out-of-order model of the ARM processor). > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
