Hi, Is this a modified Cortex-A9? If not:
I'd recommend: * setting the opLat of instructions as the ARM manual (forward cases), specially SimdFloatMultAcc which is not 1 at all. * MemRead and MemWrite are 1 in my opinion (1+Dcache hit latency ~= 2 for A9 for basic ldr, str). * Widths as being 2 can roughly estimate the perf of an A9 (in reality, there's no ROB, but it may quad-issue in some cases, issueWidth=2 is then a good average for the A9). * wbDepth for me should be max(opLat/issueLat). * L1 hit latencies are 1 or 2, L2 = 8 cycles (common values, as ARM says) Hope it helps, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2014-03-24 12:14 GMT+01:00 Stian Hvatum <[email protected]>: > Hi, > I am trying to model a single Cortex-A9 as featured in the Exynos4412 > using this configuration: http://pastebin.com/t1AU4D7H > > I wonder if someone else has modelled a similar processor or has any > knowledge about the parameters, and is able to help me with the > configuration. Using the current configuration I get some performance > discepancy compared to the real hardware. The configuration string used to > run gem5 (stable) is the following: > > {..}gem5.opt --debug-flags=Cache,MemoryAccess,Exec,-ExecSymbol > --remote-gdb-port=0 --debug-file=trace.out -d m5out/add-adc > {..}configs/example/se.py -c bin/binary --cpu-type=exynos_4412p > --mem-type=LPDDR2_S4_1066_x32 --sys-clock=400MHz --cpu-clock=1700MHz > --num-l3caches=0 --caches --l2cache --l2_assoc=16 --l1d_size=32kB > --l2_size=1MB --mem-size=2048MB > > Small loops with integer operations are slightly faster on hardware (~ > 25%), while general benchmarks are slightly faster in the simulator (~ > 25%). I wonder if this might be due to memory misconfiguration and that the > Fast-loop-mode featured in the Cortex-A9 seems to be missing from gem5? > > Best regards, > Stian Hvatum > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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