Hi Vamsi, Thanks for the suggestions. However I'm still wondering about how the communication is carried out between the L1 and L2 caches.
When an access request is made, it's packaged into a packet and send to the Sequencer to process. If it's a miss at L1, then system should try the L2 cache. How is this done? the packet is pushed into the MessageBuffer? I am kind of look for the entry point for L2 cache access here. Thanks Da On Sun, Mar 23, 2014 at 11:44 PM, Vamsi Krishna <[email protected]>wrote: > Hi Zhou Da, > > I guess you can do it. In my opinion, to do in bit hackish way, you can > try adding a member variable in existing CacheMemory class to identify type > of cache. Add and Implement functions you want specific to L2 level. You > would need to add parameter that mentions type of cache, along with size > and assoc you pass through python script (Eg: MESI_CMP_directory.py) while > creating caches. Assign the value passed through this parameter to the > "type of cache" member variable in Cache.py under RubyCache class. Just my > thought, there can be more elegant way. > > There are two memory models in gem5, classic memory model and ruby model. > src/mem/cache/* corresponds code use for classic memory model. > src/mem/ruby/* corresponds to ruby model. If you are running ruby model you > should be setting your breakpoints in src/mem/ruby*. > > Thanks & Regards, > Vamsi Krishna > > > > On Sun, Mar 23, 2014 at 10:51 PM, Zhou Da <[email protected]> wrote: > >> Hi >> >> I am not really familiar with the Ruby memory system, it looks like that >> the l1 and l2 cache are auto-generated based on the >> /src/mem/ruby/system/CacheMemory, and the .sm file just create the cache >> during compilation. >> >> Since this cache source code is shared between the l1 and l2, is it >> possible to make changes that is specific to the l2 cache? >> >> Another question is that does the source code under src/mem/cache/* even >> get used anywhere? I set up breakpoint in those files, but for the >> benchmarks I executed, it never hit those breakpoints. I am using the o3 >> cpu model. >> >> Thanks >> Da >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > > -- > Regards, > Vamsi Krishna > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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