Hello all! I am modeling a DRAM cache with bank behavior on gem5, using classic memory model. I need to add some estimateLatency and bank state update functions to the cache model. It seems that I should create a subclass of BaseCache first, say, "DRAMCache". Though I have successfully created several C++ classes for prefetcher, it turned out to be different when it comes to cache.
In the case of prefetcher, the subclass of BasePrefetcher e.g."StridePrefetcher" is implemented in C++ and added to python file. On the contrary, Cache<LRU>, although it is a subclass of "BaseCache" and contains most access behavior functions, it can not be added to python file directly. L1Cache(in Caches.py) can only inherits "BaseCache", but in fact it accesses data through all the methods of "Cache<LRU>". How does the system know which subclass to use when >1 subclasses of BaseCache coexist, if all the caches in .py file inherit "BaseCache"? Thanks!!! Jiakun Li jiakunli2010，[email protected] 2014/4/8
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
