Hi Jiakun,
There is already a fast (and representative) model of a DRAM controller in
gem5, but you will have to do some work to make use of it as a cache. It is
tailored to be “main memory”.
In general, you can choose to create a very abstract DRAM cache model by
enhancing the current gem5 cache model (with more elaborate read/write
latencies etc), or go the whole way and create a cache that interfaces with (or
is) a DRAM controller. The latter sounds awfully painful if you ask me.
In short, having a controller model is the easy bit, integrating it with a
cache is the painful part.
Andreas
From: Tao Zhang <[email protected]<mailto:[email protected]>>
Reply-To: gem5 users mailing list
<[email protected]<mailto:[email protected]>>
Date: Tuesday, 8 April 2014 16:54
To: gem5 users mailing list <[email protected]<mailto:[email protected]>>
Subject: Re: [gem5-users] Modeling a DRAM cache by creating subclass of
BaseCache or Cache?
Hi Jiakun,
FYI, as an alternative, I believe you can also find the existing DRAM cache
model in NVMain. You can contact Matt ( poremba at cse dot psu dot edu) to get
the source code from http://wiki.nvmain.org/.
thanks,
-Tao
On Tue, Apr 8, 2014 at 8:07 AM, jiakunli2010
<[email protected]<mailto:[email protected]>> wrote:
Hello all! I am modeling a DRAM cache with bank behavior on gem5, using classic
memory model. I need to add some estimateLatency and bank state update
functions to the cache model.
It seems that I should create a subclass of BaseCache first, say, "DRAMCache".
Though I have successfully created several C++ classes for prefetcher, it
turned out to be different when it comes to cache.
In the case of prefetcher, the subclass of BasePrefetcher
e.g."StridePrefetcher" is implemented in C++ and added to python file. On the
contrary, Cache<LRU>, although it is a subclass of "BaseCache" and contains
most access behavior functions, it can not be added to python file directly.
L1Cache(in Caches.py) can only inherits "BaseCache", but in fact it accesses
data through all the methods of "Cache<LRU>".
How does the system know which subclass to use when >1 subclasses of BaseCache
coexist, if all the caches in .py file inherit "BaseCache"?
Thanks!!!
Jiakun Li
jiakunli2010，[email protected]<mailto:[email protected]>
2014/4/8
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