Hi all,
I am using O3CPU with an adjacent cache line prefetcher. But when I run the
program I find the assertion in the following codes segment in function
getTimingPacket() is violated.
if (tgt_pkt->cmd == MemCmd::HardPFReq) {
// It might be possible for a writeback to arrive between
// the time the prefetch is placed in the MSHRs and when
// it's selected to send... if so, this assert will catch
// that, and then we'll have to figure out what to do.
assert(blk == NULL);
// We need to check the caches above us to verify that
// they don't have a copy of this block in the dirty state
// at the moment. Without this check we could get a stale
// copy from memory that might get used in place of the
// dirty one.
Packet snoop_pkt(tgt_pkt, true);
snoop_pkt.setExpressSnoop();
snoop_pkt.senderState = mshr;
cpuSidePort->sendTimingSnoopReq(&snoop_pkt);
I read the comments and I could imagine such a scenario. But I am a little
puzzled how to deal with that. At first I just comment the assertion since I
think it is OK to just protect the dirty line not be covered by the
prefetched data. But If I do so, another assertion will be violated in
getBusPacket().
Actually I've ever seen someone else asked similar question but no reply...
Any reply or suggestion is appreciated, thanks
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