There isn’t any delay for a TLB hit as you mention. Depending on what you configure your delays for the i and d cache, you could assume that it’s access is overlapped with the cache access.
At this point there isn’t a way to configure a delay, but that functionality could be added since translations can already be delayed because of a hardware page-table walk it probably wouldn’t be too difficult to add. Ali On Apr 14, 2014, at 7:05 PM, Zi Yan <[email protected]> wrote: > Hi All, > > I am looking at TLB translation for ARM O3 CPU. > > In src/arch/arm/tlb.cc, function TLB::translateTiming > calls translateComplete which will call translateFs/translateSe > and get the translation back to > fetch stage immediately. > > It seems that no delay is assumed for TLB hit, or > does TLB translation completely overlap with > I-Cache access? > > Is there any way to add TLB access delay in? > > Thanks. > > -- > Best Regards, > Yan Zi > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
