Hi Rodrigo,
You can definitely hack something up that determines read/write latencies per
access. That said, I would imagine that the memory controller would have to
operate based on some form of specification, essentially forcing you to assume
the worst case (see e.g. the large body of research around operating DRAM’s
outside of specification based on die-to-die variations and even on-die
variations). The fact that some operations are faster/slower may not be visible
after the controller.
Andreas
From: Rodrigo Reynolds Ramírez via gem5-users
<[email protected]<mailto:[email protected]>>
Reply-To: Rodrigo Reynolds Ramírez
<[email protected]<mailto:[email protected]>>, gem5 users mailing
list <[email protected]<mailto:[email protected]>>
Date: Thursday, 29 May 2014 00:05
To: gem5-users <[email protected]<mailto:[email protected]>>
Subject: [gem5-users] Gem5 patch 1809
Hello everyone,
I have to simulate a racetrack memory (Domain Wall Memory), because of it, I
need to have different read and write latencies but set them dynamically,
change them with every access. I sought the patches 1809 and 2072 but they set
the latencies statically.
Do you consider it is possible to change dynamically the latencies?
Thanks in advance,
Rodrigo
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