Hi guys, thanks for reply. The problem with the memory model I need to simulate is that any access could has different latencies. The idea is to improve performace with and algorithm that reduces the averange latency. I think I have to begin from patch 1809, and with the information from the block given by lru.cc estimate the latency of that access and send it to recvTimingReq. Do you think this idea is right or to simplistic? Thanks in advanceRodrigo
From: [email protected] To: [email protected]; [email protected] Date: Thu, 29 May 2014 08:43:59 +0100 Subject: Re: [gem5-users] Gem5 patch 1809 Hi Rodrigo, You can definitely hack something up that determines read/write latencies per access. That said, I would imagine that the memory controller would have to operate based on some form of specification, essentially forcing you to assume the worst case (see e.g. the large body of research around operating DRAM’s outside of specification based on die-to-die variations and even on-die variations). The fact that some operations are faster/slower may not be visible after the controller. Andreas From: Rodrigo Reynolds Ramírez via gem5-users <[email protected]> Reply-To: Rodrigo Reynolds Ramírez <[email protected]>, gem5 users mailing list <[email protected]> Date: Thursday, 29 May 2014 00:05 To: gem5-users <[email protected]> Subject: [gem5-users] Gem5 patch 1809 Hello everyone, I have to simulate a racetrack memory (Domain Wall Memory), because of it, I need to have different read and write latencies but set them dynamically, change them with every access. I sought the patches 1809 and 2072 but they set the latencies statically. Do you consider it is possible to change dynamically the latencies? Thanks in advance, Rodrigo -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
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