Hi Biswabandan, Delaying responses is not an issue as long as you schedule an event for the appropriate time to send the response back. I would guess you simply put them in a queue and do not schedule an event to get them out. If you’re waiting for n packets to show up (rather than an event), then you can end up in a situation where a master sends n – 1 requests and there will never be any progress after that.
Andreas From: biswabandan panda <[email protected]<mailto:[email protected]>> Date: Tuesday, 22 July 2014 14:48 To: Andreas Hansson <[email protected]<mailto:[email protected]>> Cc: gem5 users mailing list <[email protected]<mailto:[email protected]>> Subject: Re: [gem5-users] Responding multiple packets from the DRAM Hi, I went through the requests that were sent from L3 cache to DRAM and the responses from DRAM to L3. All the addresses (except the last 7, which end up being in the separate queue because simulate() limit reached), have been responded. So am unable to pinpoint the problem. Will delaying the responses create any issue, such that the simulation is getting over before time. On Tue, Jul 22, 2014 at 6:49 PM, Andreas Hansson <[email protected]<mailto:[email protected]>> wrote: Hi Biswabandan, It sounds like you’re forgetting to schedule an event under some circumstances. The port never drops any packets. Andreas From: biswabandan panda via gem5-users <[email protected]<mailto:[email protected]>> Reply-To: biswabandan panda <[email protected]<mailto:[email protected]>>, gem5 users mailing list <[email protected]<mailto:[email protected]>> Date: Tuesday, 22 July 2014 13:25 To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Subject: [gem5-users] Responding multiple packets from the DRAM Hi, I am making changes to the memory system in dram_ctrl.cc . Once a packet reads a data, I am not responding back immediately - but after I collect few more packets. I am storing them in a separate queue (the dram_pkt is also deleted from the respQueue). Once the separate queue becomes full, I am responding back all the packets at once using port.schedTimingResp(pkt, curTick() + latency); latency added accordingly to each packet. simulate() limit is getting reached very early - & I am guessing its because cpu got stalled waiting for a memory request that never got serviced. Is the port dropping any packets? How do I overcome this problem? Any pointer will be of great help -- thanks®ards BISWABANDAN http://www.cse.iitm.ac.in/~biswa/<http://www.cse.iitm.ac.in/%7Ebiswa/> “We might fall down, but we will never lay down. We might not be the best, but we will beat the best! We might not be at the top, but we will rise.” -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 -- thanks®ards BISWABANDAN http://www.cse.iitm.ac.in/~biswa/<http://www.cse.iitm.ac.in/%7Ebiswa/> “We might fall down, but we will never lay down. We might not be the best, but we will beat the best! We might not be at the top, but we will rise.” -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
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