Thanks Andreas,
The problem wasn't being caused by the access it seems (which was
successful using the memSidePort->sendFunctional(pkt) in cache_impl) but
by my bad handling of cacheline replacement.
By replacing the packet data allocation and handleFill(pkt, blk,
writebacks) combination I was using before with a
tags->findVictim(pkt->getAddr()) followed by a functional access
followed by a tags->insertBlock(&pkt_func, victim_blk), I've now got
this working.
Thanks again for your help,
Sam
On 2014-12-12 15:55, Andreas Hansson wrote:
Hi Sam,
Why not use the system->isMemAddr and system->getPhysMem and then do
the
access on the underlying physical memory? In essence that will short
circuit all the memory hierarchy below your cache.
Andreas
On 12/12/2014 15:52, "Sam Ainsworth via gem5-users"
<[email protected]>
wrote:
Hi,
I'm trying to use gem5 to simulate a perfect cache, where we always
have
a hit. One way I could go about this is by moving the main memory to
the
level of the L1s and change its access latency, but what I eventually
would like to do is always hit on a given set of memory locations (to
get idealised figures for optimising away those specific accesses from
lower level memory) and have everything else go through the real cache
hierarchy.
I'm having trouble getting this to work; one way which was suggested
to
me was to hack in a functional access to the address before the true
timing access, but since functional accesses don't change any state
this
causes nothing to actually happen. Similarly, forwarding the result of
that access to the timed access function on a miss, instead of doing
the
actual timed access to lower level caches, causes gem5 to go into an
infinite loop waiting on a real reply.
Has anyone implemented anything like this using gem5, and if so, do
you
have any pointers?
Thanks,
Sam
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