Hi Nizam, What do you suggest the lower-level cache should do? The UpgradeReq is ultimately there to ensure that a cache can get a line in exclusive state (E) to perform a write (M).
Andreas From: Nizamudheen Ahmed via gem5-users <[email protected]<mailto:[email protected]>> Reply-To: Nizamudheen Ahmed <[email protected]<mailto:[email protected]>>, gem5 users mailing list <[email protected]<mailto:[email protected]>> Date: Sunday, 4 January 2015 08:47 To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Subject: [gem5-users] UpgradeReq command and impact on next-level cache Hi, I am using classic memory-model in GEM5. I observed that an UpgradeReq command invalidates the line in cache. This behavior is acceptable for peer-caches in the same-level. However, i am not sure if the UpgradeReq should invalidate the cache line in the lower level caches (Caches closer to the main-memory are lower levels, in my terminology). Can someone through light on this? BR/Nizam -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
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