Hello Andreas, I am trying to find the timing specifications used in Gem5 for LPDDR3 in Micron data sheets. The datasheet specified in comments is very helpful. The only two timing constraints that I fail to find in data sheet are read-to-write delay (tRTW) and rank-to-rank switching delay (tCS). From comments, I feel that you have assumed it to be 2*tCK. Is there a reason for it to be always 2tCK across speed bins and across various DRAM types? And it would also be helpful for me if you could point me to corresponding parameter names in micron data sheet.
Thank you, -Rizwana
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