Hello All, Just wanted to follow up with my findings, I think my question is partially answered from one of the commit messages (related to introduction of tCS timing parameter):
*The delay defaults to 2*tCK for each defined memory class. Note that* *this does not correspond to one particular timing constraint, but is a* *way of modelling all the associated constraints* So, I think both tRTW and tCS are by default assumed to be 2tCK to model any associated timing constraints. Thank you, -Rizwana On Fri, Jan 30, 2015 at 5:05 PM, Rizwana Begum <[email protected]> wrote: > Hello Andreas, > > I am trying to find the timing specifications used in Gem5 for LPDDR3 in > Micron data sheets. The datasheet specified in comments is very helpful. > The only two timing constraints that I fail to find in data sheet are > read-to-write delay (tRTW) and rank-to-rank switching delay (tCS). From > comments, I feel that you have assumed it to be 2*tCK. Is there a reason > for it to be always 2tCK across speed bins and across various DRAM types? > And it would also be helpful for me if you could point me to corresponding > parameter names in micron data sheet. > > Thank you, > -Rizwana >
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