Hello All,
I am using Gem5 to simulate system CPU and DRAM frequency scaling. I am
running ARM full system simulation with detailed CPU type and LPDDR3 dram
controller with default configurations. I run simulations with android
jelly bean image. I modified Gem5 and associated DRAM controller with a new
clock domain. I set frequencies using userspace governors from kernel. So
far my simulations have been successful with good range of CPU (100MHz to
1000MHz) and DRAM frequencies (200MHz to 800MHz).
However, I am running into two issues related to "HDLcd" controller with
low memory frequencies.
1) I get following warning when memory frequency is set to 200/300MHz:
warn: HDLcd controller buffer underrun
I am guessing that the warning is coming as the Lcd buffer is not
completely filled due of low memory speeds (?).
2) With two particular frequency combinations (CPU, DRAM) = (100MHz,
300MHz) and (is 400MHz, 300MHz) I get following assertion failure.
build/ARM/dev/arm/hdlcd.cc:554: void HDLcd::endFrame(): Assertion
`pixelBufferSize == 0' failed.
The second issue doesn't occur with DDR3. Could the issue be due to lower
bandwidth of LPDDR3?
I am hoping that by adjusting either the resolution, pixel buffer size or
buffer filling rate, I might be able to solve the issues. I am not familiar
with the LCD controllers, so I am having hard time figuring out the
solution for the issues. I would appreciate any inputs from people familiar
with HDLcd, DRAM controllers or overall full system.
Thank you,
-Rizwana
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