Hi Rizwana, 1) By throttling the DRAM you are essentially starving the HDLCD and it is not able to put pixels on the screen fast enough. On a really system this is entirely unacceptable as you’d most likely end up with horrible screen distortion. Hence, it must be avoided at all cost. At the moment there is no QoS mechanism in the gem5 DRAM controller (since it opens up a tremendously large design space). In any real implementation the LCD controller would be firm real time, and you must make sure an underrun never happens.
2) That sounds unfortunate. It would be good to run that through gdb and figure out what is going wrong. It should either be happy or tell you it’s an underrun. Andreas From: Rizwana Begum via gem5-users <[email protected]<mailto:[email protected]>> Reply-To: Rizwana Begum <[email protected]<mailto:[email protected]>>, gem5 users mailing list <[email protected]<mailto:[email protected]>> Date: Thursday, 5 March 2015 16:40 To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Subject: [gem5-users] HDLcd buffer underrun with low memory frequency Hello All, I am using Gem5 to simulate system CPU and DRAM frequency scaling. I am running ARM full system simulation with detailed CPU type and LPDDR3 dram controller with default configurations. I run simulations with android jelly bean image. I modified Gem5 and associated DRAM controller with a new clock domain. I set frequencies using userspace governors from kernel. So far my simulations have been successful with good range of CPU (100MHz to 1000MHz) and DRAM frequencies (200MHz to 800MHz). However, I am running into two issues related to "HDLcd" controller with low memory frequencies. 1) I get following warning when memory frequency is set to 200/300MHz: warn: HDLcd controller buffer underrun I am guessing that the warning is coming as the Lcd buffer is not completely filled due of low memory speeds (?). 2) With two particular frequency combinations (CPU, DRAM) = (100MHz, 300MHz) and (is 400MHz, 300MHz) I get following assertion failure. build/ARM/dev/arm/hdlcd.cc:554: void HDLcd::endFrame(): Assertion `pixelBufferSize == 0' failed. The second issue doesn't occur with DDR3. Could the issue be due to lower bandwidth of LPDDR3? I am hoping that by adjusting either the resolution, pixel buffer size or buffer filling rate, I might be able to solve the issues. I am not familiar with the LCD controllers, so I am having hard time figuring out the solution for the issues. I would appreciate any inputs from people familiar with HDLcd, DRAM controllers or overall full system. Thank you, -Rizwana -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
