Hi there I have a platform with two cpu with its own icache and dcache and one classic memory. When I added CommMonitor between all the ports and try to trace the message communication, I notice that when the cpu send a timing request to data cache, the instruction cache will instead send a timing request to memory bus while data cache doesn't sent anything. And when the instruction cache eventually receive the timing response, it won't send anything to the cpu, instead, the data cache will send the timing response to cpu. I looked into the se.py and caceconfig file, the icache and dcache seems to be created separately, but according to my tracing result, they seems to be able to communicate with each other without any port. I'm very confused about how this is working, can someone help me with it?
Best, Cao _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
