Hi Cao, I think you have misinterpreted something in the traces. The only packets going between the I and D cache of a CPU are snoops.
Andreas On 05/07/2015 04:52, "gem5-users on behalf of cao2" <[email protected] on behalf of [email protected]> wrote: >Hi there > >I have a platform with two cpu with its own icache and dcache and one >classic memory. When I added CommMonitor between all the ports and try to >trace the message communication, I notice that when the cpu send a timing >request to data cache, the instruction cache will instead send a timing >request to memory bus while data cache doesn't sent anything. And when >the instruction cache eventually receive the timing response, it won't >send anything to the cpu, instead, the data cache will send the timing >response to cpu. I looked into the se.py and caceconfig file, the icache >and dcache seems to be created separately, but according to my tracing >result, they seems to be able to communicate with each other without any >port. I'm very confused about how this is working, can someone help me >with it? > >Best, >Cao >_______________________________________________ >gem5-users mailing list >[email protected] >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
