As far as I know, some architectures update CC registers at commit. Dependent instructions are are speculatively executed and then CC register is checked at commit.
Regards, Abhishek On Mon, Sep 14, 2015 at 5:29 AM, Lokesh Jindal <[email protected]> wrote: > Hello all > > > I was looking at CC register implementation in gem5 and found out that the > rename-stage of o3 cpu does not look at the number of free ccPhyregs while > determining if pipeline should stall or not. The number of free entries > only in integer and float physical register files is checked. > > > In O3CPU.py, I found a comment which says "*In typical real machines, CC > regs are not explicitly renamed (it's a side effect of int reg renaming), > so they should **never be the bottleneck here*." > > > I do not understand this comment completely. *How is the renaming of CC > registers handled in real machines, if they are not explicitly renamed like > int/float regs?* Every instruction that has "completed" execution, is not > yet "committed" and affects the condition codes would need to update the > condition codes somewhere. If it's not done through explicit cc register > renaming, what is the mechanism used in actual systems? Is there any > difference between how ARM and x86 handle this? > > > Regards > > Lokesh Jindal > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Regards, Abhishek Rajgadia Electrical Engineering, IIT Bombay
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