Hi Rodrigo, Merely an observation…with the classic memory system you can easily add an L3 and L4 cache, and as you say, changing the latencies is fairly straight forward. That said, at the moment the cache needs to have the same line size as the rest of the system. I think the best solution here is to make a “NonCoherentCache” that transparently sits in front of the memory controller(s), and can have any line size. This NonCoherentCache can be used both in classic and Ruby, since it does not interact with the coherency protocol.
What we need is for someone to take a stab at creating this class, I’d say starting with the class Cache, and then removing all the bits related to coherency. Makes sense? Andreas From: gem5-users <[email protected]<mailto:[email protected]>> on behalf of Rodrigo Reynolds Ramírez <[email protected]<mailto:[email protected]>> Reply-To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Date: Wednesday, 7 October 2015 07:33 To: gem5-users <[email protected]<mailto:[email protected]>> Subject: [gem5-users] Different Cache R/W Latency Hello Everyone, I am trying to simulate a LLC with other technology (STT-RAM), the problem is that I need different R/W latencies. I have found a couple of patches for the classic model, but I need to use Ruby. I know the access latency is divided among different parts, I need to change cell access latency. I am thinking I need to change the BankedArray.hh(cc) files, and send the access type information Read or Write. I not sure if this is the right way to get what I need. Does somebody change the access latency for the LLC in Ruby? Thanks Rodrigo ________________________________ -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
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