Hi Rodrigo, In Ruby, all the bank availability utilities are never used. You need to change the ruby generation engine (a set of python files those translate slicc files to cpp files) to enable that checkResourceAvailable function or it will never get translated into the cpp files.
Regards, Cong On Thu, Oct 15, 2015 at 11:19 AM, Rodrigo Reynolds Ramírez < [email protected]> wrote: > I have a new question regarding latencies in Ruby, I am wonder that the > methods associated to check bank availability never are used: > > void recordRequestType(CacheRequestType requestType, Addr addr); > bool checkResourceAvailable(CacheResourceType res, Addr addr); > > This methods are defined in cacheMemory.(hh|cc) but they are never used, I > think they should be used for a more realistic simulation of the cache. > What am I missing? > > Best Regards, > Rodrigo > > > ------------------------------ > From: [email protected] > To: [email protected] > Date: Wed, 7 Oct 2015 15:27:37 +0000 > > Subject: Re: [gem5-users] Different Cache R/W Latency > > Hi Andreas, > > Thanks for your answer, as you said with the classic memory system it is > pretty easy to make some changes. The problem is that I am working with > coherence protocols and I need to use Ruby. > > The NonCoherentCache seems a good solution, mainly if it could be used > with both systems and if it returns the right access depending on the > action done on the cell. It seems there is not a easy or quick way to > change the R/W latency. I was thinking that changing the BankedArray could > be the best way for change the latencies. > > Rodrigo > > ------------------------------ > From: [email protected] > To: [email protected] > Date: Wed, 7 Oct 2015 14:41:07 +0000 > Subject: Re: [gem5-users] Different Cache R/W Latency > > Hi Rodrigo, > > Merely an observation…with the classic memory system you can easily add an > L3 and L4 cache, and as you say, changing the latencies is fairly straight > forward. That said, at the moment the cache needs to have the same line > size as the rest of the system. I think the best solution here is to make a > “NonCoherentCache” that transparently sits in front of the memory > controller(s), and can have any line size. This NonCoherentCache can be > used both in classic and Ruby, since it does not interact with the > coherency protocol. > > What we need is for someone to take a stab at creating this class, I’d say > starting with the class Cache, and then removing all the bits related to > coherency. > > Makes sense? > > Andreas > > From: gem5-users <[email protected]> on behalf of Rodrigo > Reynolds Ramírez <[email protected]> > Reply-To: gem5 users mailing list <[email protected]> > Date: Wednesday, 7 October 2015 07:33 > To: gem5-users <[email protected]> > Subject: [gem5-users] Different Cache R/W Latency > > Hello Everyone, > > I am trying to simulate a LLC with other technology (STT-RAM), the problem > is that I need different R/W latencies. I have found a couple of patches > for the classic model, but I need to use Ruby. > > I know the access latency is divided among different parts, I need to > change cell access latency. I am thinking I need to change the > BankedArray.hh(cc) files, and send the access type information Read or > Write. I not sure if this is the right way to get what I need. Does > somebody change the access latency for the LLC in Ruby? > > Thanks > Rodrigo > > ------------------------------ > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > _______________________________________________ gem5-users mailing list > [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > _______________________________________________ gem5-users mailing list > [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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