Hi, I am trying to implement DRAM cache. I have created a non-coherent module for the LLC which connects via non-coherent bus to the main memory. The setup works till the write queue is not full for the DRAM cache controller. When it gets full, it rejects the responses coming from the main memory for which the recvTimingResp code has to return false. The non-coherent bus doesn't accept recvTimingResp returning false saying "Illegal to block responses leads to deadlock". The alternative I tried out was to block the request (retry) in case of miss in DRAM cache but due to some reason it doesn't work out.
Is there any way to solve the problem? I want to retry the responses on failure on a given attempt. Thanks, Debiprasanna Sahoo
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