Hi Debiprasanna, There is no fundamental reason why responses cannot block, it is merely a convention (when requests and responses shared the same logical channel in the port it was needed to avoid message-dependent deadlocks). I sounds like you have a perfectly valid use-case for blocking responses, and perhaps it is time to properly add support for the blocking. Are you happy to give it a go and post a patch? It should be more or less copy&paste from the request code.
By the way, please also post the DRAM cache. Did you based it on the existing Cache module? Thanks, Andreas From: gem5-users <[email protected]<mailto:[email protected]>> on behalf of Debiprasanna Sahoo <[email protected]<mailto:[email protected]>> Reply-To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Date: Tuesday, 22 December 2015 at 11:55 To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Subject: [gem5-users] Illegal to block responses Hi, I am trying to implement DRAM cache. I have created a non-coherent module for the LLC which connects via non-coherent bus to the main memory. The setup works till the write queue is not full for the DRAM cache controller. When it gets full, it rejects the responses coming from the main memory for which the recvTimingResp code has to return false. The non-coherent bus doesn't accept recvTimingResp returning false saying "Illegal to block responses leads to deadlock". The alternative I tried out was to block the request (retry) in case of miss in DRAM cache but due to some reason it doesn't work out. Is there any way to solve the problem? I want to retry the responses on failure on a given attempt. Thanks, Debiprasanna Sahoo IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
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