Felipe,
The same phenomenon for the ICache can also be explained by timing.
Bigger DCache means branches dependent on loads will (generally) be
resolved quicker so less instructions will be fetched on the wrong path.
Arthur.
Le 08/04/2016 21:23, Felipe de Azevedo Piovezan a écrit :
Hi Arthur,
Thank you for the reply. I'm indeed using the O3CPU, so your
hypothesis makes a lot of sense. But this only accounts for the data
cache, and I'm also observing this difference in the instruction cache.
I will try running my simulations with different processors and check
what happens then.
On 8 April 2016 at 13:15, Arthur Perais <[email protected]
<mailto:[email protected]>> wrote:
Hi Felipe,
I'm gonna assume that you run O3CPU or Minor. Changing cache size
changes timing. Changing timing may change the number of loads
that get their data from the Store Queue (hence don't access the
cache).
If you run atomic or timing, however, I'm not exactly sure how to
explain it.
Arthur.
Le 08/04/2016 18:12, Felipe de Azevedo Piovezan a écrit :
Hi all,
One quick question about gem5:
How come when we run a program twice but with different cache
sizes (say 2KB and 4KB) we get a different number of total
accesses (on both caches)?
This should be a property of the program and it should also be
independent of the architecture used.
Thanks
--
Felipe
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Arthur Perais
INRIA Bretagne Atlantique
Bâtiment 12E, Bureau E303, Campus de Beaulieu
35042 Rennes, France
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INRIA Bretagne Atlantique
Bâtiment 12E, Bureau E303, Campus de Beaulieu
35042 Rennes, France
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