Hi Tanmay, The short answer is yes: Simply use the AddrRange striping and hashing functionality.
The long answer: Each cache is responsible for an AddrRange, and typically this is imply a [start:end] range. However, the AddrRange class also support striping, e.g. [start:end] with bit [x:y] == z. It also allows using XOR hashing as part of the latter mapping. The actual steering of packets is done by the Xbar class. This means you can place a CoherentXBar between your L2s and L3s, then create as many L3s as you want and interleave them using the AddrRange assigned to each one of them. Note that you have to be a bit careful as the cache currently is not taking the interleaving into account in its tag computation. This is a known issue and should ultimately be addressed. For example, there is clearly no entropy left in the bits used for interleaving, so using them for a set-associative cache lookup will effectively lead to underuse of certain ways. Andreas From: gem5-users <[email protected]<mailto:[email protected]>> on behalf of Tanmay Gangwani <[email protected]<mailto:[email protected]>> Reply-To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Date: Sunday, 23 October 2016 at 03:51 To: "[email protected]<mailto:[email protected]>" <[email protected]<mailto:[email protected]>> Subject: [gem5-users] L3 in Classical Model Is it possible to split up a single L3 into different slices/regions (similar to Xeon processors) in the classical memory model? Thanks. IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
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