Hello, I'm happy to announce that RISC-V is now supported by gem5! Currently it supports single-threaded workloads in SE mode and binaries compiled with riscv64-unknown-elf-*.
There are two bugs that need to be fixed: binaries compiled with riscv64-unknown-gnu-linux-* will not run (see comment chain on Oct. 20, 2016 in http://reviews.m5sim.org/r/3624/ for more information), and some memory accesses can rarely cross a cache boundary which causes the O3 model to crash (see the first comment chain in http://reviews.m5sim.org/r/3693/ for more information). Beyond that, here's what needs to be implemented to bring RISC-V to completion: - The TLB code was copied from MIPS, but it may need to be re-implemented to fit the description in RISC-V's privileged ISA reference ( https://riscv.org/specifications/privileged-isa/). - Multithreaded workload support needs to be added (RISC-V may need to be added to m5threads). - Support for FS mode needs to be added. This will at the very least mean adding all of the CSRs defined in the privileged ISA reference and implementing the ERET and EBREAK instructions so privileged code works properly. Thanks to everyone who reviewed the code and helped get it included into gem5! Regards, Alec Roelke
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