Hi Reza, This is handled by the port interface between the cache and the main memory. For instance, at the DRAM controller, every request calls recvTimingReq(). You may learn something from this chapter of my book: http://learning.gem5.org/book/part2/memoryobject.html. The caches and the memory controllers are just MemObj's.
Cheers, Jason On Wed, Feb 8, 2017 at 8:57 AM Mohammad Reza Jokar <[email protected]> wrote: > Dear all, > > When we experience a cache miss at last level cache, we should send a > request to main memory and ask for the missed block. I was wondering if you > could help me find a file or function that does send requests to main > memory (and receive responses from that.) > > > Thank you. > Reza > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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