Hi Jason, Thank you for your response and reference to your book. I will read that. I'm using NVmain as memory type. In this case, should I look into gem5 source files or NVmain source files? I'm looking for a file/function that checks if the access to last level cache is a miss, then sends the request to main memory.
Thank you. Reza On Wed, Feb 8, 2017 at 9:04 AM, Jason Lowe-Power <[email protected]> wrote: > Hi Reza, > > This is handled by the port interface between the cache and the main > memory. For instance, at the DRAM controller, every request calls > recvTimingReq(). You may learn something from this chapter of my book: > http://learning.gem5.org/book/part2/memoryobject.html. The caches and the > memory controllers are just MemObj's. > > Cheers, > Jason > > On Wed, Feb 8, 2017 at 8:57 AM Mohammad Reza Jokar <[email protected]> > wrote: > >> Dear all, >> >> When we experience a cache miss at last level cache, we should send a >> request to main memory and ask for the missed block. I was wondering if you >> could help me find a file or function that does send requests to main >> memory (and receive responses from that.) >> >> >> Thank you. >> Reza >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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