Hi everyone !
I am going to simulate two ARM cores in gem5 . And I have to achieve
some intercommunication between two cores so I should do some modification
in gem5's source code. But I can't find the place where gem5 simulates
multi-cores's intercommunication via shared memory or something else . Can
anyone help me with where gem5's cpu's intercommunication is ?
Or I can use SMT to simulate the dual-core architecture . But could I
modify the thread's intercommunication in cpu models with SMT such as o3
cpu ?
Thanks!
Qingran Wang
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