Yes, I'll do that. Thank you. Subhankar Pal
On Mar 13, 2017 4:47 AM, "Andreas Hansson" <[email protected]> wrote: Hi Subhankar, I think the best option would be to resolve any outstanding issues to properly support the AddrRange interleaving in the cache. It has definitely worked in the past, at least with the caveats I mentioned earlier. Could you do a bit more digging? Andreas From: Subhankar Pal <[email protected]> Date: Sunday, 12 March 2017 at 04:24 To: gem5 users mailing list <[email protected]>, Andreas Hansson < [email protected]> Subject: Re: [gem5-users] Caches with interleaved address ranges connected to HBM Hi Andreas, Thank you for answering my question. I looked at MemConfig and I see that it assigns interleaved address ranges to memory controllers. The major difference I found with respect to assigning interleaved address ranges to a cache was that the cache seems to accept a Vector of address ranges, whereas the mem controller takes a single address range, which causes different functions to get called in the C++ code (src/base/addr_range.hh). I get a fatal error if I try to assign an address range to a cache with some interleave bits. It seems to have the requirement of* # address ranges = 2^(# of interleave bits)*. Say, I want to split and interleave my address range between four caches (# of interleave bits = 2). I am thinking of trying to manually append partial address ranges to each of the four caches (populate the Vector of address ranges) to create interleaved pattern, instead of using the interleave mechanism present in the C++ codebase. Can you tell me if that would work? Thank you! Subhankar Pal On March 11, 2017 at 1:43:16 PM, Andreas Hansson ([email protected]) wrote: Hi Subhankar, Each cache has an address range, and it is by configuring these ranges that you can create a number of interleaved caches. I would suggest having a look at configs/common/MemConfig for an example of how this is done. Each range supports “simple” interleaving by simply using a stride size, and it also supports XOR-based hashing. Something you need to keep in mind is that the caches currently are not taking the interleaving into account when determining the set/way. This is something that has been a “todo” for quite some time, and unfortunately we have not yet created a simple and elegant way of doing this. In the case of simple interleaving you should simply ignore those bits in the cache to avoid a “loss of entropy”. For the hashing it gets more complicated, as no specific bits can be dropped. I hope this e-mail can perhaps also start a discussion on how to sensibly accommodate more advanced interleaving, and do so without the aforementioned caveats. If anyone has suggestions for a good design, please speak up. It would be good to make sure that it “just works”. Andreas From: gem5-users <[email protected]> on behalf of Subhankar Pal < [email protected]> Reply-To: gem5 users mailing list <[email protected]> Date: Saturday, 11 March 2017 at 01:56 To: "[email protected]" <[email protected]> Subject: [gem5-users] Caches with interleaved address ranges connected to HBM Hi all, I am trying to build a system where processors are connected (via a crossbar) to multiple caches having interleaved address ranges. These caches are each connected to one channel of an HBM. How do I interleave the address ranges over the caches and how do I connect them to an HBM memory? Your help is highly appreciated! Subhankar Pal IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ______________________________ _________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
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