Hi, I am trying to simulate the GDDR5 model (GDDR5_4000_2x32) in src/mem/DRAMCtrl.py (using MemConfig) and initially I got an error saying tCS is not assigned. I worked around that by borrowing values from an earlier changelist. Now, I am hitting the assertion: *gem5.opt: build/ARM/mem/dram_ctrl.cc:2107: void DRAMCtrl::Rank::processWakeUpEvent(): Assertion `(pwrState == PWR_ACT_PDN) || (pwrState == PWR_PRE_PDN) || (pwrState == PWR_SREF)' failed.*
Can someone help me on how to fix this error? Thank you! Subhankar Pal
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