I think you can do that by generating multiple requests along with the main request to the dram. You can do that in memory controller or the cpu side. Specific details depends upon how many cache lines you require and their addresses. But i think its not that much difficult. See the trace of some high spatial locality benchmark like libquantum, so from the trace you can reverse engineer how to generate consecutive memory addresses.
On Apr 29, 2017 3:04 AM, "Muzamil Rafique" <[email protected]> wrote: Hi All, When we have a miss in LLC and found that address in row-buffer (row currently open) in main memory, how can we bring multiple cache-lines residing in that row buffer (along with requested one) in to caches? Is there currently any support available in gem5? Thanks Muzamil _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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