Hello, I'm a new gem5 user and simulating the coherent protocol of MESI with two level of caches. I see on the ProtocolTrace log file that several transition of the same address can occur at the same cycle. See below:
7263 0 L2Cache Unblock MT_SB>SS [0x400, line 0x400] 7263 0 L2Cache L1_GETS SS>SS [0x400, line 0x400] 7263 0 L2Cache L1_GETS SS>SS [0x400, line 0x400] 7263 0 L2Cache L1_GET_INSTR SS>SS [0x400, line 0x400] All these 4 messages are accepted and influence the state machine (even though it seems like the state kept the same (SS>SS) the requestor has added to the sharer list). I was expecting to have only 1 event per cycle that will impact the state machine. What/Where is the best way to define this restriction (1 message at a clock) on All cache level's ? Thanks, Hagai
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