Hi Hagai, You can limit the transitions per cycle with the option "transitions_per_cycle" on each controller.
Note that some of the transitions are "logical" and not what a real implementation would do. This is why the default transitions per cycle is higher. FOr instance, in your example, the 4 transitions are really just one "real" transition, but uses more logical transitions for simplicity of implementation. There is some support in Ruby for tracking resources by tagging each transition. See MOESI_AMD_Base-CorePair.sm for an example of how to do this. Jason On Mon, Jul 24, 2017 at 2:39 AM Hagai David <[email protected]> wrote: > Hello, > > > > I'm a new gem5 user and simulating the coherent protocol of MESI with two > level of caches. > > I see on the ProtocolTrace log file that several transition of the same > address can occur at the same cycle. > > See below: > > > > 7263 0 L2Cache Unblock MT_SB>SS > [0x400, line 0x400] > > 7263 0 L2Cache L1_GETS SS>SS > [0x400, line 0x400] > > 7263 0 L2Cache L1_GETS SS>SS > [0x400, line 0x400] > > 7263 0 L2Cache L1_GET_INSTR SS>SS [0x400, > line 0x400] > > > > All these 4 messages are accepted and influence the state machine (even > though it seems like the state kept the same (SS>SS) the requestor has > added to the sharer list). > > I was expecting to have only 1 event per cycle that will impact the state > machine. > > > > What/Where is the best way to define this restriction (1 message at a > clock) on All cache level's ? > > > > Thanks, > > > > Hagai > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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