Hi Everyone, As the CPU is ARMv8, is anyone aware of any architectural constraints as to why the instructions are not being executed from Instruction-SPM ? Secondly in BaseCPU.py, there are _uncached_master_port. Can I connect the SPM to the _uncached_master_port, or is it for interrupts only ?
Regards Yasir From: gem5-users [mailto:[email protected]] On Behalf Of Qureshi Yasir Mahmood Sent: 01 December 2017 16:45 To: gem5 users mailing list <[email protected]> Subject: [gem5-users] Instructions Access from Instruction Scratch Pad (I-SPM) Hello All, I have recently been working on adding both data and instruction scratch Pad (SPM) in GEM5 FS simulation. I was able to add both of them alongside with having L1-I and L1-D cache. The memory system now looks as in figure at https://imgur.com/a/wUtUX Since I am using FS mode, I can access the D-SPM and I-SPM using open("/dev/mem") and mmap(). I-SPM is connected to both the instruction as well as data port, so that we can write the program to it through data port and execute and read through instruction port. To test this, I compiled a helloworld program as a library which does not print anything, but just returns an integer value. We access this library through dlopen and the function in the library through dlsym. Then through function pointer we copied the function to the I-SPM. Finally we jumped to the function in I-SPM through a function pointer call. After this the program gets stuck and does not proceed. In the stats file I can see the write accesses (to copy the function to) the SPM issued by cpu.data, but I don't see any read cpu.inst access to I-SPM. Can someone suggest why the CPU does not read the I-SPM when I jump to the function in it ? NOTE: When using mmap() I do enable PROT_EXEC to mark I-SPM as executable memory region. Regards Yasir
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