Hi Jason, Is there as specific reason as to why you can’t connect O3 ports directly to the crossbar ? I have added Scratchpad memories at the same level as L1. I used NonCoherent Xbar to connect the scratch pad and L1 and them connected the Xbar to the CPU ports.
The system worked fine for all CPU models, except for O3, and returned the same error as reported in this thread. Thanks Yasir From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Jason Lowe-Power Sent: 14 March 2017 14:19 To: gem5 users mailing list <gem5-users@gem5.org> Subject: Re: [gem5-users] Error Simulating Simple Config. file with DerivO3CPU This is because the O3 ports cannot be directly connected to a crossbar. You need to use a cache between the ports and the membus. See the two_level script. Jason On Mon, Mar 13, 2017, 5:00 PM Muzamil Rafique <muzamil.ravian...@gmail.com<mailto:muzamil.ravian...@gmail.com>> wrote: Hi All, I tried to simulate simple.py with DerivO3 CPU and got the following error: command line: build/X86/gem5.opt configs/tutorial/simple.py Beginning simulation! info: Entering event queue @ 0. Starting simulation... gem5.opt: build/X86/mem/xbar.cc:190: bool BaseXBar::Layer<SrcType, DstType>::tryTiming(SrcType*) [with SrcType = SlavePort; DstType = MasterPort]: Assertion `std::find(waitingForLayer.begin(), waitingForLayer.end(), src_port) == waitingForLayer.end()' failed. Program aborted at tick 5734000 It works fine with TimingSimpleCPU but giving error with DerivO3CPU. Any ideas why this error pops up, which was not the case previously? Thanks Muzamil _______________________________________________ gem5-users mailing list gem5-users@gem5.org<mailto:gem5-users@gem5.org> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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