Hi all, As part of my Master's I am investigating effects of disabling cache coherence on OS-development.
For my research I need access to x86's CLFLUSH instruction which is currently not implemented in Gem5. So, I tried to follow the INVLPG instruction, which has a similar structure (two byte opcode, one mem8 operand). If I didn't miss anything, a possible implementation of CLFLUSH comprises introducing a new microop (like "tia" for INVLPG) that calls a function on an ExecContext object. That function would forward the actual work to its associated CPU, which can finally use "FlushReq" memory packets. Handling of FlushReqs isn't yet implemented in conventional caches neither, so I would need to add that implementation, too. Does that sound reasonable? Or am I missing something important? Is there actually any work ongoing on implementing CLFLUSH? Thanks for your help! Best, Maximilian Stein TU Dresden E-Mail: maximilian.st...@tu-dresden.de <mailto:maximilian.st...@tu-dresden.de>
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