Hey Swapnil, Thanks for your mail! That's definitely helping me.
Best, Maximilian Am 17. Januar 2018 18:29:16 MEZ schrieb Swapnil Haria <[email protected]>: >Hey Maximilian, > >I have recently submitted a patch for this. You can find it here: >https://gem5-review.googlesource.com/c/public/gem5/+/7401 > >This patch allows CLFLUSH, CLFLUSHOPT and CLWB to be used with the >classic >caches. > >Cheers, >Swapnil Haria, >PhD Candidate, >Dept of Computer Sciences, >University of Wisconsin-Madison > >On Fri, Jan 12, 2018 at 8:22 AM, Maximilian Stein < >[email protected]> wrote: > >> Hi all, >> >> As part of my Master's I am investigating effects of disabling cache >> coherence on OS-development. >> >> For my research I need access to x86's CLFLUSH instruction which is >> currently not implemented in Gem5. So, I tried to follow the INVLPG >> instruction, which has a similar structure (two byte opcode, one mem8 >> operand). >> >> If I didn't miss anything, a possible implementation of CLFLUSH >comprises >> introducing a new microop (like "tia" for INVLPG) that calls a >function on >> an ExecContext object. That function would forward the actual work to >its >> associated CPU, which can finally use "FlushReq" memory packets. >Handling >> of FlushReqs isn't yet implemented in conventional caches neither, so >I >> would need to add that implementation, too. >> >> Does that sound reasonable? Or am I missing something important? >> >> Is there actually any work ongoing on implementing CLFLUSH? >> >> Thanks for your help! >> >> Best, >> >> Maximilian Stein >> TU Dresden >> E-Mail: [email protected] >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
