Hi Chen, Yes. All gem5 SimObjects are in one process. They all share a global event queue where they can enqueue events (e.g., fetch at instruction, send a new memory request, etc.). The event queue executes one event at a time (in host/real time), but in simulated time many events can happen at the same *simulator tick*. For instance, every CPU could issue a fetch at the same tick. To ensure consistency within the simulated guest system, you have to use some kind of protocol (e.g., coherence for keeping caches consistent).
Jason On Thu, May 17, 2018 at 10:28 AM Chen Zou <zine.ch...@gmail.com> wrote: > Hi Jason, > > Thanks a lot for your reply. > > But I do have a follow-up question. > > If I create multiple CPU, they all can issue memory requests to the memory > system. Do they live in the same single-threaded process? > > Is it the event queue that serializes the request (issued from the > TraceCPU, or issued by a cache to another cache) according to the ticks and > thus guarantee the consistency? > > Regards, > > Chen > > On 05/14/2018 04:07 PM, Jason Lowe-Power wrote: > > Hi Chen, > > To answer your question simply: No. > > In almost all cases, gem5 is not thread safe. There are a few very special > circumstances where you can use multiple threads, but you have to be very > careful when doing so. > > You can still playback "multithreaded" traces in gem5 by creating multiple > simulated trace CPUs and using a different file for each trace CPU. > > Also, to answer your other question, no, the mailing list does not send an > email to the original author by default. I think you can change this > setting in mailman, though. > > Jason > > ----------- > Jason Lowe-Power > Assistant Professor, Computer Science Department > University of California, Davis > 3049 Kemper Hall > https://faculty.engineering.ucdavis.edu/lowepower/ > > > > On Thu, May 10, 2018 at 3:12 PM Chen Zou <zine.ch...@gmail.com> wrote: > >> Hi all, >> >> This is similar to the previous email I sent to the user list, but I made >> some updates. >> >> I am inclined to write my own trace-driver to replay some multi-threaded >> traces on the simulated memory hierarchy (let's say #L1D = #L1I = #L2 = >> #threads_in_the_trace and a shared L3). It seems that L3 could be added >> with a CoherentBus. >> >> If possible, I would like to initiate several threads (say, one pthread >> per thread_in_the_trace) to replay the trace to accelerate the simulation. >> I am worried if the classic cache model is thread-safe, especially if >> there is a shared L3 in the hierarchy. Thanks in advance. >> >> BTW, does the mail-list send the email to the original author? I didn't >> receive my previous email. >> >> Regards, >> Chen >> >> _______________________________________________ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > _______________________________________________ > gem5-users mailing > listgem5-users@gem5.orghttp://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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