Hi Gabe, Jason, Are those x86 SIMD SSE arithmetic instructions take only one cycle as latency? I looked into the FuncUnitConfig.py and seems like the op lats for the SIMD functional units are not defined, so I assumed it takes value of 1 by default.
I am not really familiar with x86 SIMD extension, so maybe this question is more related to x86 ISA in general. Thanks. On Thu, May 24, 2018 at 9:52 AM, Jason Lowe-Power <ja...@lowepower.com> wrote: > Hi Tariq, > > It wold be great if you could review Gabe's patch on gerrit. Since it > works for you, giving it a +1 or a +2 would be appropriate. > > Cheers, > Jason > > On Wed, May 23, 2018 at 5:56 PM Tariq Azmy <tariqslaye...@gmail.com> > wrote: > >> Thanks Gabe. Yeah it does not impact the program but it's just that the >> statistic is incorrect. >> >> By the way, I applied the patch and stats now shows correct micro-ops >> entries. >> >> Appreciate your help. Thanks again >> >> On Wed, May 23, 2018 at 6:51 PM, Gabe Black <gabebl...@google.com> wrote: >> >>> Yep, those microops aren't given a operand class, and so the isa parser >>> is guessing and making the FloatAddOp. I haven't really tested this beyond >>> making sure it compiles, but here's a patch that might get this working for >>> you. >>> >>> https://gem5-review.googlesource.com/c/public/gem5/+/10541 >>> >>> Gabe >>> >>> On Wed, May 23, 2018 at 4:13 PM, Gabe Black <gabebl...@google.com> >>> wrote: >>> >>>> I'm confident they aren't implemented with floating point add. It's >>>> likely either that the microops are misclassified, or they're unimplemented >>>> and printing a warning, but the fact that they don't actually do any math >>>> isn't impacting your program for whatever reason. I'll take a quick look. >>>> >>>> Gabe >>>> >>>> On Wed, May 23, 2018 at 2:07 PM, Tariq Azmy <tariqslaye...@gmail.com> >>>> wrote: >>>> >>>>> Hi, >>>>> >>>>> I wrote simple code that does simple floating point multiplication and >>>>> division operation and from the assembly, I can see there are MULSS and >>>>> DIVSS instructions. But after I ran the simulation on gem5 and looked at >>>>> the stat.txt, I can only see the entries in >>>>> system.cpu.iq.FU_type_0::FloatAdd, >>>>> where as the entries in FloatMul and FloatDiv remains 0. >>>>> >>>>> If I understand correctly, these stats refer to the micro-ops. Does >>>>> that mean the MULSS and DIVSS instruction are broken down and executed >>>>> with >>>>> floating point Add? >>>>> >>>>> Thanks >>>>> >>>>> >>>>> _______________________________________________ >>>>> gem5-users mailing list >>>>> gem5-users@gem5.org >>>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>>>> >>>> >>>> >>> >>> _______________________________________________ >>> gem5-users mailing list >>> gem5-users@gem5.org >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>> >> >> _______________________________________________ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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