Hi Abishek, Everything is possible, it all depends on the cache policy. I think the default behavior in gem5 is a write-back cache, and I am not sure if any other policies are implemented (Can someone else confirm?). A write-back cache only writes the data back upon eviction, unlike a write-trough cache were all levels are updated at write time. So, for your example: if both L1 and L2 are write-back caches, then the block in L2 gets updated after eviction from L1. Only later, when the block gets evicted from L2, then the content is written in main-memory.
Best regards On Sun, Aug 5, 2018 at 3:59 PM Abhishek Singh < [email protected]> wrote: > Hi Timon, > I had one question eviction of write back. > What happens when a dirty block is evicted from L1 cache. Does it check L2 > cache updates the content of that block in L2 and then goes to memory and > update contents in memory ? > > On Thu, Aug 2, 2018 at 4:04 AM Timon Evenblij <[email protected]> > wrote: > >> Hi Abishek, >> >> No, for this case, MSHRs (miss status handling registers) exists. These >> are registers that keep track of missed cache accesses (in your case packet >> 1 that misses in L1), so the cache can be freed to reply to other accesses >> (packet 2) while waiting for the answer of the miss (packet 1 gets answered >> from L2 or even further away). >> >> Best regards, >> >> Timon >> >> On Thu, Aug 2, 2018 at 2:30 AM Abhishek Singh < >> [email protected]> wrote: >> >>> My question is simple if there are two packets wants to access L1 cache >>> in a system of 2 level cache and cpu is o3. Will packet 2 has to wait for >>> packet 1 to get its response(packet 1) from L2 in case of L1 cache miss and >>> L2 cache hit? >>> What happen if its L2 miss? >>> >> _______________________________________________ >>> gem5-users mailing list >>> [email protected] >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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