Hello Nikos, Many thanks for your reply. After reading a bit, I also came to that conclusion, however I must confess that I am somehow clueless about how to do that with the configuration that I am using. The diagram of the system I am trying to mount is the following: |
As I am accessing the main memory directly from the accelerator, I need to perform address translation. For that purpose, I am instantiating an ArmTLB and connecting it with the accelerator. When I try to run the system, I get the error: fatal: fatal condition !stage2Mmu occurred: Table walker must have a valid stage-2 MMU To make it easier, I attach the python wrapper of the accelerator (CacheComputeUnit.py) and configuration file (run-ccs.py) that I am using. Again, many thanks for your help! 😊 Best, João Vieira |
from m5.params import * from m5.proxy import * from MemObject import MemObject # from Process import EmulatedDriver from ArmTLB import ArmTLB
class CacheComputeUnit(MemObject):
type = 'CacheComputeUnit'
cxx_header = "ccs/cache_compute_unit.hh"
# memory ports
cpu_port = SlavePort("CPU side port, receives requests")
mem_port = MasterPort("Memory side port, sends requests")
# CCS' PI
ccs_addr = Param.Addr(0x200000000, "Points to the beginning of the region where the CCS is mapped")
reg_size = Param.MemorySize('4kB', "Size of the CCS PI")
reg_late = Param.Cycles(10, "Latency to access CCS' PI")
ccs_width = Param.Unsigned(512, "Width of the CCS in bits")
system = Param.System(Parent.any, "system object")
# TLB
tlb = Param.ArmTLB(ArmTLB(), "TLB/MMU to walk page table")
# class CacheComputeUnitDriver(EmulatedDriver):
# type = "CacheComputeUnitDriver"
# cxx_header = "ccs/cache_compute_unit.hh"
# filename = "cache_compute_unit"
#
# hardware = Param.CacheComputeUnit("The cache compute unit hardware")
import m5
from m5.objects import *
from caches import *
# program to execute
binary = 'tests/test-progs/ccs/ccs'
#binary = 'tests/test-progs/hello/bin/arm/linux/hello'
# simulation system
system = System()
# clock configuration
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '3.6GHz'
system.clk_domain.voltage_domain = VoltageDomain()
# memory configuration
system.mem_mode = 'timing'
system.mem_ranges = [AddrRange('8GB')]
# create CPU
system.cpu = DerivO3CPU()
# create device selector
system.devsel = DeviceSelect()
# connect device selector with CPU data cache port
system.devsel.cpu_port = system.cpu.dcache_port
# create CCU
system.ccu = CacheComputeUnit(ccs_addr = 0x80000000)
# system.ccu_driver = CacheComputeUnitDriver(hardware = system.ccu)
# connect CCU with device selector
system.devsel.ccs_port = system.ccu.cpu_port
# create L1 caches
system.cpu.icache = L1Cache()
system.cpu.dcache = L1Cache()
# connect L1 instruction cache to the CPU
system.cpu.icache.cpu_side = system.cpu.icache_port
# connect L1 memory cache to device selector
system.cpu.dcache.cpu_side = system.devsel.mem_port
# create L1 to L2 interconnect
system.l2bus = L2XBar()
# link L1 with interconnect
system.cpu.icache.mem_side = system.l2bus.slave
system.cpu.dcache.mem_side = system.l2bus.slave
# create L2 cache
system.l2cache = L2Cache()
# link L2 cache with L1 to L2 interconnect
system.l2cache.cpu_side = system.l2bus.master
# create L3 cache
system.l3cache = L3Cache()
# link L3 cache with L2 cache
system.l3cache.cpu_side = system.l2cache.mem_side
# create memory bus
system.membus = SystemXBar()
# connect L3 cache with memory bus
system.l3cache.mem_side = system.membus.slave
# create interrupt controller
system.cpu.createInterruptController()
# connect interruptions and IO with memory bus (required by X86)
if m5.defines.buildEnv['TARGET_ISA'] == "x86":
system.cpu.interrupts[0].pio = system.membus.master
system.cpu.interrupts[0].int_master = system.membus.slave
system.cpu.interrupts[0].int_slave = system.membus.master
# connect special port to allow read/write memory
system.system_port = system.membus.slave
# create memory controller
system.mem_ctrl = DDR3_1600_8x8()
# connect memory controller with memory bus
system.mem_ctrl.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master
# simulation procedures
process = Process()
process.cmd = [binary]
system.cpu.workload = process
system.cpu.createThreads()
root = Root(full_system = False, system = system)
m5.instantiate()
system.cpu.workload[0].map(0x80000000, 0x80000000, 4096)
print("========== Beginning simulation ==========")
exit_event = m5.simulate()
print('Exiting @ tick {} because {}' .format(m5.curTick(), exit_event.getCause()))
|
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