Hello Nikos,

Thank you a lot! In fact your advice solved this problem.

Best,
JV

> No dia 06/08/2018, às 18:46, Nikos Nikoleris <[email protected]> 
> escreveu:
> 
> Hi Joao,
>  
> I believe you also need to instantiate a stage2 mmu. You can have a look at 
> how we do it for the Arm cores in src/cpu/BaseCPU.py. There you will find the 
> param
> dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans").
> You need something along the same line for your accelerator.
>  
> Nikos
>  
>  
> From: gem5-users <[email protected] 
> <mailto:[email protected]>> on behalf of João Miguel Morgado 
> Pereira Vieira <[email protected] 
> <mailto:[email protected]>>
> Reply-To: gem5 users mailing list <[email protected] 
> <mailto:[email protected]>>
> Date: Monday, 6 August 2018 at 14:24
> To: gem5 users mailing list <[email protected] <mailto:[email protected]>>
> Subject: Re: [gem5-users] ArmTLB - Table walker must have a valid stage-2 MMU
>  
> Hello Nikos, 
>  
> Many thanks for your reply.
>  
> After reading a bit, I also came to that conclusion, however I must confess 
> that I am somehow clueless about how to do that with the configuration that I 
> am using. The diagram of the system I am trying to mount is the following:
>  
> <image001.png>
>  
> As I am accessing the main memory directly from the accelerator, I need to 
> perform address translation. For that purpose, I am instantiating an ArmTLB 
> and connecting it with the accelerator. When I try to run the system, I get 
> the error: 
>  
> fatal: fatal condition !stage2Mmu occurred: Table walker must have a valid 
> stage-2 MMU
>  
> To make it easier, I attach the python wrapper of the accelerator 
> (CacheComputeUnit.py) and configuration file (run-ccs.py) that I am using.
>  
> Again, many thanks for your help! 😊
>  
> Best,
> João Vieira
>  
>  
> 
> 
> No dia 03/08/2018, às 19:54, Nikos Nikoleris <[email protected] 
> <mailto:[email protected]>> escreveu:
>  
> Hi Joao,
> 
> I can't really tell where the problem is but when you configure your system 
> you have to make sure that the cores have a stage 2 MMU for both the data 
> (dstage2_mmu) and the instruction side (istage2_mmu).
> 
> Nikos
> 
> On 03/08/2018, 15:28, "gem5-users on behalf of João Miguel Morgado Pereira 
> Vieira" <[email protected] <mailto:[email protected]> on 
> behalf of [email protected] 
> <mailto:[email protected]>> wrote:
> 
>    Hi guys,
> 
>    In SE mode, I have a memory mapped accelerator and I have to perform 
> virtual to physical address translation to access the data in memory. I took 
> as inspiration the work of powerjg, (thank you a lot for sharing your code, 
> by the way). However I am using the ARM model, instead of the x86, which 
> means that I should use the ArmTLB instead of the X86TLB. I instantiate it 
> and pass it as parameter to my accelerator. When I use the X86 model (and 
> consequently the X86TLB) everything goes fine, but when I try to instantiate 
> the ArmTLB, I simply get: fatal: fatal condition !stage2Mmu occurred: Table 
> walker must have a valid stage-2 MMU.
> 
>    Does someone came across with this problem and can give me a hint about 
> how to solve it?
> 
>    Thank you very much in advance.
> 
>    Best,
>    João Vieira
> 
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