Hi, You need to know what are you going to test (perfomance/power). Take in to account that different architectures support different applications. Define the demands of the system and then do what Ciro said, find an existed SoC which match your requirements and create your processor similar to it.
Best Regards, Georgios Bousdras PhD Researchers - Embedded Systems BEAMS - ULB > On 3 Dec 2018, at 13:36, 杜东 <[email protected]> wrote: > > Hi guys, > > I am using GEM5 ARM with the Minor CPU (specifically, HPI mode). > The default configuration is : > Core: 4GHz > TLB: 256 entries I/D TLB > L1 I/D cache: 1 cycle (data/tag/response) > L2 I/D cache: 13 cycles for data and tag access > memory type: DDR3_1600_8x8. > > This default configuration seems too great? > I am not sure whether real devices can achieve the performance, especially > 1 cycle L1 cache access. > > So do you have any recommendation on the configurations? > Any comments are welcomed! > > Dong > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
