Hello everyone, I have a question regarding stats in multi-core SE simulation. The following stats: Stats::Vector masterReadAccesses Stats::Vector masterWriteAccesses in dram_ctrl.hh/.cc gives different results in stats.txt file. masterReadAccesses gives stats results like:
system.mem_ctrls.masterReadAccesses::.switch_cpus_10.inst 70 # Per-master read serviced memory accesses system.mem_ctrls.masterReadAccesses::.switch_cpus_10.data 3397616 # Per-master read serviced memory accesses system.mem_ctrls.masterReadAccesses::.switch_cpus_11.inst 53 # Per-master read serviced memory accesses system.mem_ctrls.masterReadAccesses::.switch_cpus_11.data 1232898 # Per-master read serviced memory accesses system.mem_ctrls.masterReadAccesses::.switch_cpus_12.inst 356 # Per-master read serviced memory accesses system.mem_ctrls.masterReadAccesses::.switch_cpus_12.data 2684152 # Per-master read serviced memory accesses system.mem_ctrls.masterReadAccesses::.switch_cpus_13.inst 2074 # Per-master read serviced memory accesses system.mem_ctrls.masterReadAccesses::.switch_cpus_13.data 489603 # Per-master read serviced memory accesses while masterWriteAccesses gives only information about writebacks. Why can't it trace back to the masterId() which originally generates write request (just like read does)? The corresponding code is in dram_ctrl.cc line # 531-533 system.mem_ctrls.masterWriteAccesses::.writebacks 2318583 # Per-master write serviced memory accesses Any help would be greatly appreciated :) Thanks Sam
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